In typical state machines, the present state latches switch to the next state only after the next state input signals have changed by a significant proportion of the supply voltage. Thus, for example, in an NMOS embodiment powered by a +5 volt supply, the present state latches will change state only after the next state input signals have changed about, 2.5 volts relative to the supply rails. In this form, this rate of change is largely dependent upon the size of the transistors in the drivers of the next state input signals. However, increasing the size of these transistors also increases the respective gate capacitances, requiring additional drive capability in the next state input logic transistors. This in turn impacts the size of the present state decode logic transistors and ultimately the output drive of the present state latches. Thus, speed of operation is obtained at the expense of silicon area and power dissipation.